Articles

Design of a System-on-Chip Architecture Backbone for European Defence Applications

First activity of the WP1 was to collect system requirements for the various targeted product. This has been done covering the following applications:

  • Optronic
  • Software Defined Radio
  • Missile
  • Modem
  • Navigation and guidance

This analysis has been proceeded examining the architecture dedicated for each application. Huge activities have been performed to identify the commonalities and the required resources in order to define an ideal architecture able to host all the applications.

On one hand, WP1 delivered to WP4 the input necessary for the development of the HW building blocks, on the other hand it defined the test vehicle architecture for the WP5.

Finally, WP1 identified the processing part candidate to an evaluation within Corsair SoC chip and started to develop the modules based on existing algorithm and basic building blocks.

Main functions were: filtering, interpolation, decimation, motion analysis and specific modulation.

 

 

For more information about this Work Package please contact the Project Leader.

Safety Computing Platform

In the WP2, a general architectural concept for certifiable military SoC based on collected system requirements for a military SoC has been elaborated. Concepts for the mitigation/improvement of the proposed SoC architecture have also been defined. Therefore, the safety analysis methods "Failure Mode and Effect Analysis" (FMEA) and "Fault Tree Analysis" (FTA) were described and a FMEA was done for all SoC modules. Furthermore an example of an FTA was performed. The outcome of the FMEA and the FTA were some improvement and mitigation measures. The general safety standard IEC 61508 was analyzed and compared with DO-254 and the relevant aspects concerning SoC were extracted and an IEC 61508 certification strategy for SoC devices was established.

Moreover a technology evaluation analyzed different FPGA technologies (Flash, SRAM FPGAs) for certification in military systems involved in safety, and the following features were evaluated:

  • Long-time data retention for Flash-based FPGAs;
  • Power-interruption for SRAM-based FPGAs;
  • Radiation robustness.

 In parallel, a classification of the Hard Macros for different complexity ranges was done:

  • Simple Hard Macro;
  • Complex Hard Macro;
  • Embedded Microsystem.

The available Hard-IPs were analyzed regarding the requirements from certification documents and a certification proposals for the Hard IP were given. An Embedded Microsystem was identified as a potential candidate for safety critical applications, only the processor performance without FPU is a major limitation. For the SRAM Based SoC FPGAs major risks were identified, and this risks have to be mitigated before this SoC are planned for a safety critical application.

Another sub-work package made a tools evaluation to analyze Certification documents regarding Tools & Methodologies. Certification document were analyzed regarding the usage of tools and methodologies and requirements were extracted. The market was analyzed and promising candidates were selected, compared with Design Assurance Level (identified with a capital letter as in DO-254), and shown in the following table (due to commercial reason, only a number is reported to identify the tool, for more information please contact the Project Leader):

Tools \ DAL

A

B

C

D

E

1

Risks

Risks

Risks

Possible

Possible

2

Risks

Risks

Risks

Possible

Possible

3

Possible with manual review

Possible with manual review

Possible

Possible

Possible

4

Risks

Risks

Risks

Possible

Possible

5

Risks

Risks

Possible

Possible

Possible

6

Possible

Possible

Possible

Possible

Possible

Possible means that the tools could be used.
Risks mean the tools could be used but the certification is not ensured. There are risks to achieved using such tools.

Another objective of the WP2 was to manage use of IP-Building-Blocks into the certification processes and two kinds of IP were considered:

  • Reuse IPs;
  • COTS IPs.

As a conclusion, COTS IP compliant to SoC requirements are available but deeper analysis is required due to data available often linked to NDA between industrial partners and IP providers.

Finally three demonstrators were implemented to cover a maximum of design and verification tools and methodologies analyzed in whole WP:

  • The first demonstrator consists of two parts. The first part is an AXI4 isolator, a design IP that contains functionality generated by the Tool #6. The second part is an AXI4 BFM, a verification IP used for the verification of the AXI4 isolator.
  • The second demonstrator is a design IP and consists of an I2C COTS IP and thus covers the COTS IP aspects.
  • The third demonstrator is a verification IP for a MIL-STD-1553 design IP core. It is implemented in UVM and makes use of the advanced verification methodologies Constrained Random Simulation, Coverage Driven Verification and Assertion-Based Verification.

 

 

For more information about this Work Package please contact the Project Leader.

Programmable Hardware blocks for advanced/flexible System-on-Chip

Three HW building blocks were developed inside the WP4. Mainly exchanges occurred between end user and STM and Menta to provide requirements from the WP1 results. Some of them have been introduced in the modules before their prototyping in 2013.

The three test vehicles have been manufactured and delivered for characterization purpose and potential improvement before their integration within the WP5 test vehicle.

ST test-vehicle prototyped two different configurable IPs on STM 65nm LP technology:

                                • CuBrick mask-programmable logic;
                                • PiCoGA, run-time programmable datapath.

Both the IPs have been evaluated for what is concerning the functionality and the performance, achieving results in line with expectation.

For the CuBrick mask-programmable solution, the activity confirmed the coherence and the alignment of all the CAD views with silicon results. On the design under verification, the IP reaches a working frequency of about 300MHz in nominal condition and a peak of about 350MHz over-driving the core-supply at 1.3V.

For the PiCoGA run-time programmable datapath, silicon prototyping confirmed the correctness of the CAD views with respect to both the functional specification and the timing characterization of the boundary annotated on the Liberty view. Concerning the performance evaluation, the working frequency of the device should be estimated about 100-150MHz on nominal conditions for mid-high complexity applications, while under highly-congested routing conditions the speed can slow down to about 50MHz.

No specific improvements have been required for the IPs, but a request to extend the programming flow of PiCoGA has been considered useful to overcome the area limitation of the WP5 test-vehicle. For that, PiCoGA programming flow has been improved adding an emulation model to allow synthesizing the code on standard FPGA.

PiCoGA emulation model is intended as a simple and quick way to emulate/simulate PiCoGA without the overhead of managing the bitstream-accurate model. This can allow designers to verify the system integration of the PiCoGA Interface with less computational requirements or to prototype the system on third-party FPGAs, moreover PiCoGA emulation model is much lighter in terms of complexity and it does not require any change on the PiCoGA Interface, which is the same for emulation and hard-macro integration.

The next figure shows the basic concept of the PiCoGA emulation model. Starting from the Griffy-C description of the PiCoGA operations, the same tool which generates the bitstream also provides a behavioural VHDL model. This model shall be compiled with the standard PiCoGA Interface and the emulation library of native Griffy-C operators. The resulting design can be used for both simulation and synthesis on third-party FPGA devices.

WP4 Griffy-C

 

The model has been verified on HDL simulator using test-cases pre-verified on the hardware device, thus ensuring the functionality and the correspondence of the boundary signals with respect to the hardware device.

One of the major results is the eFPGA physical implementation on STM CMOS065LP silicon process and it covers:

  • The eFPGA specification;
  • Implementation of different basic blocks: eLBs, DSP and embedded memory block;
  • The custom cells designed for CMOS065LP process to improve area density;
  • The specific floorplan technique due to regular structure;
  • The verifications done;

After the manufacturing step by STM, a PCB was specifically designed and manufactured to evaluate and characterize eFPGA test-vehicle. Menta realized a completed verification including functional verification and associated performances. Results are the following:

  • All basic blocks like eLB, DSP and embedded memories are functional;
  • Custom blocks like the memory bit cell and multiplexer are correct;
  • The bitstream sending and reading during operations is also validated;
  • The correlation between Menta programming software and hardware is correct because all mapped applications tested were correctly achieved on eFPGA.

The eFPGA implementation was constraint to 100 MHz maximum frequency for bitstream sending and reading and also for application. All measures give result at least 100MHz of maximum frequency so both timing and power performances are in line with implementation.

 

 

For more information about this Work Package please contact the Project Leader.

SECURITY in FPGAs – High Assurance Crypto in Programmables Platforms

The WP3 has been one of the trickiest Work Packages regarding the topics handled and the potential sensitive information which could appear during the discussion. Nevertheless, the partners involved have succeeded in defining the requirements of the next product generation and also the reconfigurable structure (FPGA). This has also been the opportunity to exchange information between various countries and to feed this back to the respective national authority. The members of WP3 have converged on the requirements, on the evaluation to be performed and the associated test.

The project has also been an opportunity to work closely with the selected FPGA provider (Xilinx) which has opened their design centre for the evaluation team. A lot of design information has been provided which allow the CESTI to perform their evaluation and to allow the other members to perform their implementation and testing. As at the end of the project, all the requirements claimed by Xilinx have been correctly verified.

From the developer point of view, the isolation design (clustering approach) is operational, but was not yet industrial due to the low maturity of the tools. The tools supporting isolation design contained many bugs, required several steps and labour-intensive operations to successfully use the technology. Limited trials with the latest version of the tools show strong improvement on the tools necessary to perform and verify isolation designs.

 

 

 

For more information about this Work Package please contact the Project Leader.

Development and Evaluation of an encapsulated SoC that embeds a Programmable Hard macro

To cover the initials objectives the partners have specified the requirements of the test chip and have selected one of the HW building blocks developed within the WP4. Embedded FPGA has been selected for the CORSAIR test chip.

To verify the goodness of the test chip by Dolphin Integration and Menta, and to test the software by End-Users, all partners participated to development of a test board realized by SED (below figure). This board is composed of a CORSAIR chip as well as an additional FPGA to support the CORSAIR in all applications required by partners and to ensure the interfacing with both inside and outside the board, to allow maximum flexibility.

Regarding the initial objectives we have fully covered the foundry access road. The following steps have been successfully reached:

  • Design kit and library delivery by design house;
  • Front-end design support using the 65nmtechnology;
  • Back-end design;
  • Manufacturing thanks to MyMPW approach;
  • Packaging;
  • Component deliveries.

Regarding the eFPGA the CORSAIR SoC chip development validated the capabilities of the supply chain to deliver chip integrating such structure. In term of performances, the eFPGA is a real promising technology as demonstrated by the evaluation performed. Tools are operational and they are able to reach an high filling rate ratio. Although the chip was only a test vehicle with less constraint than a real product, the complete flow has been executed demonstrating the relevance of the foundry access. This was one of the major results of EDASOC projects.

Test board

Test board for CORSAIR chip.

 

 

For more information about this Work Package please contact the Project Leader.