To cover the initials objectives the partners have specified the requirements of the test chip and have selected one of the HW building blocks developed within the WP4. Embedded FPGA has been selected for the CORSAIR test chip.
To verify the goodness of the test chip by Dolphin Integration and Menta, and to test the software by End-Users, all partners participated to development of a test board realized by SED (below figure). This board is composed of a CORSAIR chip as well as an additional FPGA to support the CORSAIR in all applications required by partners and to ensure the interfacing with both inside and outside the board, to allow maximum flexibility.
Regarding the initial objectives we have fully covered the foundry access road. The following steps have been successfully reached:
- Design kit and library delivery by design house;
- Front-end design support using the 65nmtechnology;
- Back-end design;
- Manufacturing thanks to MyMPW approach;
- Component deliveries.
Regarding the eFPGA the CORSAIR SoC chip development validated the capabilities of the supply chain to deliver chip integrating such structure. In term of performances, the eFPGA is a real promising technology as demonstrated by the evaluation performed. Tools are operational and they are able to reach an high filling rate ratio. Although the chip was only a test vehicle with less constraint than a real product, the complete flow has been executed demonstrating the relevance of the foundry access. This was one of the major results of EDASOC projects.
Test board for CORSAIR chip.
For more information about this Work Package please contact the Project Leader.